1. Field of the Invention
The present invention relates to a built-in test circuit, more particularly a PCI Express physical layer built-in test circuit capable of detecting command symbols to automatically compensate loopback latency.
2. Description of the Prior Art
In the development of personal computer systems and peripheral devices, bandwidth and speed requirements of the interconnect interface are increasing. The load of a conventional PCI device becomes greater, therefore the third generation input/output (3GIO) has gradually replaced PCI interface to provide the greater bandwidth requirement. The third generation input/output (3GIO) is also known as a PCI Express interface. Those skilled in the arts know that the PCI Express technology utilizes a higher operational clock and applies more data lanes to improve efficiency. The first generation PCI Express technology can provide 2.5 GB per second of bandwidth in a one directional data lane, which is great improvement for the efficiency of the computer system especially in pattern processing.
The PCI Express device operates at a high-speed transmission where volume of data transmission is high. As the accuracy of signals must be maintained, a conventional built-in self test (BIST) method tests the accuracy of symbols received by the PCI Express device. A test pattern generator (TPG) and an output response analysis (ORA) are built-in to a lane under test. Please refer to FIG. 1. FIG. 1 illustrates a diagram of a conventional PCI Express physical layer built-in self test circuit architecture 100. The architecture 100 includes a pattern generator 102, an elastic buffer receiver 104, a pattern register 106, a pattern comparison module 108, and a lane under test 110. The pattern generator 102 generates a test pattern to the lane under test 110 and the pattern register 106, then the elastic buffer receiver 104 receives and transmits the test patterns via the lane under test 110 to the pattern comparison module 108, and the pattern register 106 temporarily stores and transmits the test patterns in a predetermined time to the pattern comparison 108. The test pattern received by the elastic buffer receiver 104 and the test pattern stored in the pattern register 106 are compared, the pattern comparison module 108 determines whether the lane under test 110 correctly transmits the test pattern generated by the pattern generator 102.
The conventional built-in self test circuit architecture 100 does not require an external automatically test equipment (ATE) to generate a test vector, also it is not required by the ATE to analyze test results. Therefore the test bandwidth requirement is less than general test methods, and test speed is not limited by the ATE speed hence it is more efficient. However, the lane under test 110 of the PCI Express includes a plurality of loopback paths, which also means that time required by the test patterns to pass through the lane under test 110 is not constant, so that the loopback latency cannot be predicted. Therefore the storage capacity of the pattern register 106 must be sufficiently large to compensate the loopback latency. Furthermore, the built-in self test circuit architecture 100 will be affected by phase jitter which causes errors in the pattern comparison module 108. Moreover, the storage capacity of the pattern register 106 must be restricted; therefore when the loopback latency becomes too great, the built-in self test architecture 100 will not operate accurately.